Serially connected memory systems, such as HLNAND™ developed by MOSAID Technologies Inc., are configured with a data interface, sometimes called a data bus, that originates at a controller, is serially connected to a number of memory devices, typically in a daisy-chain ring, and returns to the controller. The data interface may include one or more bits, and is used to carry out both read and write operations for all of the serially connected memory devices. While this serial configuration provides a flexible and high-performance memory system, it presents a number of difficulties under some operating conditions.
When operating conditions require reading and writing to the memory system at the same time, the read and write operations contend for use of the same data interface. For example, if the write operation takes an extended period of time, the write operation must be interrupted to allow the read operation to occur, or else the read operation must be delayed while the write operation is completed. If both read and write operations are required at the same time, particularly if either or both occupies a significant portion of the data interface bandwidth, bus contention can result in significant delays and inconvenience to the user.
One solution to this problem is to truncate a write signal at the target memory device instead of propagating the write signal around the rest of the ring, thereby leaving the data interface free to carry a read signal back to the controller from either the same memory device or a downstream memory device. This method allows concurrent read and write on the same data interface of a daisy-chain memory array without bus contention, but only when the target of the read operation is downstream from the target of the write operation in the direction of data communication around the ring. The read and write may be performed on the same target device if the target device has independent input and output ports. If the read and write requests are directed to random devices in the ring, it should be understood that there is roughly a 50% probability that the controller will be able to arrange a read operation and a concurrent write operation, resulting in roughly a 50% increase in data interface bandwidth usage. Further advantages in bandwidth usage can be realized if the controller schedules read and write operations appropriately, for example by holding write requests in a queue until a read request is addressed to a downstream device and then processing the two at the same time. However, this arrangement further increases the complexity of the controller, and may require a significant amount of memory to maintain a potentially large queue. In addition, this arrangement still requires delaying some operations, which may be undesirable in some applications where continuous reading and writing may both be desired at the same time.
Therefore, there is a need for a serial memory array capable of performing concurrent read and write operations and having a simple design.
There is also a need for a serial memory array capable of performing concurrent read and write operations independently of the physical addresses of the targets of the read and write operations.
There is also a need for a method of using a single data interface to perform concurrent read and write operations on a serial memory array.